In the flash EEPROM (Electrically Erasable Programmable Read Only Memories) including split gate FET devices, for example, including polysilicon source and wordline electrodes, the level of the voltage required to be applied,to the control gate in a split gate field effect transistor (FET) flash memory device structure is critical and is affected by the profile of the polysilicon electrode, also referred to as a wordline spacer which functions as the control gate in a split gate flash memory configuration. For example, the polysilicon spacer (electrode) profile can affect the series resistance and hence the electrical stability of the control gate, for example, including altering hot electron injection processes or Fowler-Nordheim tunneling processes which adversely affect the stability of the control gate thereby adversely affecting the reliability of write and erase operations, both processes essential to the reliable operation of flash memory devices. For example, the electric field strength present at a polysilicon electrode/gate oxide (tunnel oxide) interface, determines the desired flow of current in response to applied voltages to accomplish write and erase operations.
In the formation of polysilicon word and source line electrodes in conjunction with a split gate FET device, for example employing a self-aligned polysilicon wordline electrode in a split gate FET configuration, a consistent and predictable profile of the polysilicon structure is critical to proper electrical functioning of the device. As design rules have decreased to below about 0.25 micron technology, achieving acceptable etching profiles of the polysilicon structures has become increasingly difficult due to several hard to control RIE etching phenomena including polymeric residue formation and micro-trenching as a result of secondary plasma ion bombardment. In addition, problems are presented in RIE etching processes where different doping levels of polysilicon are present causing variable etching rates.
One particular problem in polysilicon RIE etching processes, for example in the formation of a self aligned polysilicon structure, is preferential etching and accumulation of polymeric RIE etching residues at an upper portion of the polysilicon structure to produce a fence or raised portion at outer edges of the upper portion of the polysilicon structure. For example, during prior art RIE etching processes to form self aligned polysilicon wordline electrodes, the formation of fences which are composed of a hardmask and polysilicon layer at an outer edge of the upper portion of the polysilicon structure has been a recurring problem which undesirably alters the etching profile of the polysilicon structure to cause undesired variations in polysilicon electrical resistances and presents the potential for causing electrical shorting to subsequently formed overlying wiring, for example, bit lines.
There is therefore a need in the split gate FET device processing art to develop improved etching processes to improve the etching profile of a self-aligned polysilicon wordline electrode structure and thereby improve the yield and reliable operation of split gate FET devices including flash memory devices.
It is therefore an object of the invention to provide an improved etching process to improve the etching profile of a self-aligned polysilicon wordline electrode structure and thereby improve the yield and reliable operation of split gate FET devices including flash memory devices, while overcoming other deficiencies and shortcomings of the prior art.